Research, Innovation & Development (RID).Innovation and Development Accelerator (IDA).Information & Communication Technology Services (ICT).Corporate Engagement & International Relations (CEIRD).Sam Nujoma Marine & Coastal Resources Research Centre.Quality Assurance and Management (CEQUAM).Centre for Innovation in Learning and Teaching (CILT). ![]() Grants Management and Resource Mobilization.Faculty of Health Sciences & Veterinary Medicine.School of Humanities, Society & Development.School of Business Management, Governance & Economics.School of Engineering & the Built Environment.School of Agriculture & Fisheries Sciences.Faculty of Agriculture, Engineering & Natural Sciences.Online Support for Distance Education/Part-time Studies.Distance/Part-time Postgraduate Programmes.Distance/Part-time Undergraduate Programmes.Distance Education/Part-time Requirements.In MICRO 25: Proceedings of the 25th annual international symposium on Microarchitecture, pages 81-91, Los Alamitos, CA, USA, 1992. Executing compressed programs on an embedded risc architecture. The SPARC Architecture Manual Version 9, 2000. ![]() Berkeley, University of California Press, 1967. In Proceedings of 5th Berkeley Symposium on Mathematical Statistics and Probability, pages 281-297. Some methods for classification and analysis of multivariate observations. Storage assignment to decrease code size. In MICRO 30: Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, pages 194-203, Washington, DC, USA, 1997. Improving code density using compression techniques. ![]() PowerPC Code Compression Utility User's Manual Version 3.0, 1998. ![]() A method for the construction of minimum-redundancy codes. Spec cpu2000: Measuring cpu performance in the new millennium. Intel Architecture Software Developers Manual Volume 2: Instruction Set Reference, 1997. In PLDI '99: Proceedings of the ACM SIGPLAN 1999 conference on Programming language design and implementation, pages 139-149, New York, NY, USA, 1999. Enhanced code compression for embedded risc processors. The results demonstrate that a small number of distinct binary ISAs can provide reasonably good fits across a broad range of application benchmarks. This paper focuses on opcode compression through a set of benchmark-driven experiments to identify clusters of near optimal ISA fits. The PRECISE (Processor Register Extensions for Collapsed Instruction Set Encoding) methodology addresses the data type, opcode, and register access components of the instruction stream. This paper explores the potential for reducing instruction pressure through a combination of variable length binary instruction set and Huffman encoding to reduce the average number of bits per instruction compared to a typical fixed-length fixed-code binary instruction set. L1 instruction cache and processor pin bandwidth are examples of direct resource costs imposed by the instruction access demand of a processor architecture. Instruction pressure is the level of time, space, and power required to manage the instruction stream to support high-speed execution of modern multicore general processor and embedded controller based computing.
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